http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021257362-A1

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filingDate 2021-05-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9bdf6ac48d33250539bcf2a945abdb31
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publicationDate 2021-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2021257362-A1
titleOfInvention Enlarging Spacer Thickness by Forming a Dielectric Layer Over a Recessed Interlayer Dielectric
abstract An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.
priorityDate 2016-03-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 26.