http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021257356-A1

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filingDate 2020-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bfa96342aadc9be48c44d8cc1936cb62
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publicationDate 2021-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2021257356-A1
titleOfInvention Inter-level connection for multi-layer structures
abstract Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.
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Total number of triples: 24.