| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76832
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-2481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53295
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76819
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B53-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B61-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| filingDate |
2020-01-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a8ac2a5842aea96cd48c4f67bc65fd07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_acfa2a2b00c39d29e37aa25815c30014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1e54046696d117523d3ea706bfb860b9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a39d38738d9934e074863ef296cac5f7 |
| publicationDate |
2021-08-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2021242216-A1 |
| titleOfInvention |
Interconnect and memory structures having reduced topography variation formed in the beol |
| abstract |
Interconnect structures or memory structures are provided in the BEOL in which topography variation is reduced. Reduced topography variation is achieved by providing a structure that includes a first dielectric capping layer that has a planar topmost surface and/or a second dielectric capping layer that has a planar topmost surface. The first dielectric capping layer has a non-planar bottom surface that contacts both a recessed surface of an interconnect dielectric material layer and a planar topmost surface of at least one electrically conductive structure that is embedded in the interconnect dielectric material layer. |
| priorityDate |
2020-01-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |