http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021241842-A1

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filingDate 2020-02-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5b846d42fec9e2888d65444b88efa3ed
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publicationDate 2021-08-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2021241842-A1
titleOfInvention Microelectronic device testing, and associated methods, devices, and systems
abstract Memory devices are disclosed. A memory device may include a memory array including a number of column planes and at least one circuit coupled to the memory array. The at least one circuit may generate test result data for a column address for each column plane of the number of column planes. The at least one circuit may further convert the test result data to a first result responsive to two or more of the column planes failing the test. The at least one circuit may also convert the test result data to a second result responsive to no column planes failing the test. Further, the at least one circuit may convert the test result data to a third result responsive to one column plane failing the test. The third result may identify the one column plane. Methods of testing a memory device, and electronic systems are also disclosed.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11514977-B2
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