http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021184683-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M3-157 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M1-0064 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0816 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03H1-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M3-155 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M3-156 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M1-0025 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M1-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M1-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-133 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M3-158 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-087 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-087 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-081 |
| filingDate | 2020-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9b1ec53f87bdd62d305b6f5ee0a72a93 |
| publicationDate | 2021-06-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2021184683-A1 |
| titleOfInvention | Clock distribution circuit using adjustable phase control and voltage converter including the same |
| abstract | A clock distribution circuit including a Phase Locked Loop (PLL), a first Phase Detecting and Converting (PDC) circuit, a second PDC circuit, and a clock generating and compensating (CGC)circuit may be provided. The PLL may generate reference clock signals. The first PDC circuit may generate input phase difference voltages based on phase differences between respective pairs of two reference clock signals among the reference clock signals. The second PDC circuit may generate output phase difference voltages based on phase differences between respective pairs of two power switching signals among power switching signals received from external switching regulators. The CGC circuit may generate input clock signals provided to the plurality of external switching regulators by shifting phases of the reference clock signals, and additionally control a phase of at least one of the input clock signals based on the input phase difference voltages and the output phase difference voltages. |
| priorityDate | 2019-12-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 60.