| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02356
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02148
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02159
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02321
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02181 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 |
| filingDate |
2019-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_520b251dc86ad612f5255dea142c6ba1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9653c4283fde0d28d58bba5c270655b8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd572fa04204f8b27c6393b7545a862c |
| publicationDate |
2021-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2021119050-A1 |
| titleOfInvention |
Ferroelectric Semiconductor Device and Method |
| abstract |
A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications. |
| priorityDate |
2019-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |