http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021083685-A1

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filingDate 2020-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_49d458bdd87e39844856d9729ff3d2e9
publicationDate 2021-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2021083685-A1
titleOfInvention Pipelined successive approximation register analog-to-digital converter and method of analog-to-digital conversion
abstract A pipelined successive approximation register analog-to-digital converter ( 2 ), SAR ADC, comprises a first SAR ADC stage ( 4 ); an inter-stage amplifier ( 6 ) for amplifying an analog residue from the first SAR ADC stage; and a second SAR ADC stage ( 8 ) input from the inter-stage amplifier, wherein the inter-stage amplifier ( 6 ) comprises one or more MOS transistors ( 16, 18 ), wherein the source and drain terminals of each of the one or more MOS transistors ( 16, 18 ) are connected to each other and may be toggled between ground and a supply voltage.
priorityDate 2019-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 20.