Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_58054227722081749d7e8e121924a5c8 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-764 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40114 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28568 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31053 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53266 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11556 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11565 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11582 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11565 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582 |
filingDate |
2020-02-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_22e186b5bc39377bfd4dfeef7f12ac95 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2d7bb6d57d6716e0f4bac928d8fa16ec http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_326bb51510107253c09b90546a636fdc |
publicationDate |
2021-03-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2021066339-A1 |
titleOfInvention |
Semiconductor memory device and method of manufacturing the same |
abstract |
According to one embodiment, a semiconductor memory device includes: a plurality of first interconnect layers including first and second conductors; a second interconnect layer arranged above the first interconnect layers; a third interconnect layer arranged adjacently to the second interconnect layer; a first pillar passing through the first interconnect layers and the second interconnect layer; a second pillar passing through the first interconnect layers and the third interconnect layer; and a third pillar arranged between the second interconnect layer and the third interconnect layer and passing through the first interconnect layers. The second conductor covers a top surface and a bottom surface of the first conductor, and a side surface of an end portion of the first conductor. |
priorityDate |
2019-09-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |