| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d80f1040809503e54509c871ba828f75 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02675
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02609
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02074
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30625
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02639
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-321
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02675
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02595
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306 |
| filingDate |
2019-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_afc7ef693cb8c6a5a7acacfa83a7d1eb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a025c3f5a97666d836bd4b05bb7c0489
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0196c0ca2a9c17451ac5c9970db2cd2b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a56351ab29999f45bf37654d299650f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3910a5ad1e653cb018d98d925e1c9568 |
| publicationDate |
2021-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2021043516-A1 |
| titleOfInvention |
Multi-dimensional planes of logic and memory formation using single crystal silicon orientations |
| abstract |
A method of forming transistor devices includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of field effect transistors; depositing a first insulator layer on the first transistor plane; forming holes in the first insulator layer using a first etch mask; depositing a first layer of polycrystalline silicon on the first insulator layer, the first layer of polycrystalline filling the holes and covering the first insulator layer; and annealing the first layer of polycrystalline silicon using laser heating, the laser heating creating regions of single-crystal silicon. A top surface of the first transistor plane is a top surface of a stack of silicon formed by epitaxial growth. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11700723-B2 |
| priorityDate |
2019-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |