http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021020659-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_03fc41c4e41cbd2c6eafe96ab0c9ce14 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-2275 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-2273 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-50 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-2257 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11597 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-223 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11587 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11597 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11587 |
| filingDate | 2020-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2d6db4c4db3d2e09d61cefdb40fa599e |
| publicationDate | 2021-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2021020659-A1 |
| titleOfInvention | Three-Dimensional Ferroelectric Random-Access Memory (FeRAM) |
| abstract | A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor. |
| priorityDate | 2019-05-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 64.