http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021013326-A1

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d80f1040809503e54509c871ba828f75
classificationCPCAdditional http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2029-7858
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0669
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
filingDate 2019-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3910a5ad1e653cb018d98d925e1c9568
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_afc7ef693cb8c6a5a7acacfa83a7d1eb
publicationDate 2021-01-14-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2021013326-A1
titleOfInvention Multiple planes of transistors with different transistor architectures to enhance 3d logic and memory circuits
abstract Microfabrication of a collection of transistor types on multiple transistor planes in which both HV (high voltage transistors) and LV (low-voltage transistors) stacks are designed on a single substrate. As high voltage transistors require higher drain-source voltages (Vds), higher gate voltages (Vg), and thus higher Vt (threshold voltage), and relatively thicker 3D gate oxide thicknesses, circuits made as described herein provide multiple different threshold voltages devices for both low voltage and high voltage devices for NMOS and PMOS, with multiple different gate oxide thickness values to enable multiple transistor planes for 3D devices.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11133310-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021351180-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11552080-B2
priorityDate 2019-07-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

Predicate Subject
isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419548998
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419524915
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419520403
http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID159433
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419579069
http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID82832
http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID93091
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID452908191
http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID23969
http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID5352426
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419559477
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419559362
http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID3084099
http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID23963
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419522015

Total number of triples: 48.