| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_543f81076a0539dda3718ef97249ec66 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-09
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02167
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0223
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10894 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| filingDate |
2020-03-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1185413d865e3ac0a238715cd299b106
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4eddee2febca50ed279991db777f7b5b |
| publicationDate |
2020-07-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2020227420-A1 |
| titleOfInvention |
Semiconductor device and method for fabricating the same |
| abstract |
A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a logic region; forming a stack structure on the memory region and a gate structure on the logic region; forming a first cap layer on the stack structure and the gate structure; performing an oxidation process to form an oxide layer on the first cap layer; forming a second cap layer on the oxide layer; and removing part of the second cap layer, part of the oxide layer, and part of the first cap layer on the logic region to form a spacer adjacent to the gate structure. |
| priorityDate |
2018-04-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |