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filingDate 2019-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1079ff3198180fb6b2812cc573370930
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publicationDate 2020-07-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2020211615-A1
titleOfInvention Memory device having shared read/write access line for 2-transistor vertical memory cell
abstract Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.
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