| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0802 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G04F10-005
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-095 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G04F10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-095
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-083 |
| filingDate |
2019-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1ba95b84a00c6421993f192d864a105a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_624f8d3beaf08b7bcd2a09b474c51ac5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_96a168d1c4cbf94a86e6138ff14d06f3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ee288ab0b16999e2931c6508635f5dac
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b2edede9984d5db733f4735c8585dfae |
| publicationDate |
2020-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2020201263-A1 |
| titleOfInvention |
Adaptive time-to-digital converter and method |
| abstract |
Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by a delay. Gate circuitry generates a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired delay. |
| priorityDate |
2018-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |