| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5e829b93e1bdf87272f2aaf3baaaa0f4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c8fbf590463d3518a746d90a6a2c1c34 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2885 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31051
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31138
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0332
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0214
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02118 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-532 |
| filingDate |
2020-02-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f558d2620574c53d046c77947451cc01 |
| publicationDate |
2020-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2020176268-A1 |
| titleOfInvention |
Semiconductor structure |
| abstract |
A semiconductor structure is provided. The semiconductor structure includes: a substrate; and a functional layer, on the substrate. The substrate includes a device region. The semiconductor structure further includes a plurality of discrete sidewall spacers, on the functional layer in the device region. Adjacent sidewall spacers are spaced apart by a first gap and a second gap, and the first gap and the second gap are alternately arranged. The semiconductor structure further includes: a core layer on a sidewall surface of one side of the sidewall spacer; a second opening in the functional layer at a bottom of the second gap exposed by the sidewall spacer and the core layer; and a first opening in the functional layer at a bottom of the first gap. The core layer is disposed in the second gap. |
| priorityDate |
2017-09-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |