| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1469
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14634
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-768 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-146
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2019-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c8bacfcd111c74355b1d13fb774dc5b7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d1fbc87a5b4493645e9ccd11b76867b3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_599e235d2d23445764ad8b62734eeede
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_82f19c1905b3a293e46ad5b375b8ae99
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1c32412e7fab76f0f7d794b81ef115dd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d596f9658ba663553d3976f504a5ca27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3e0d9795c1dd7fbcb00bf54e3fa46923 |
| publicationDate |
2020-04-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2020127027-A1 |
| titleOfInvention |
Interconnect Structure for Stacked Device and Method |
| abstract |
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer. |
| priorityDate |
2013-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |