Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76202 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42368 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5286 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66659 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02304 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66681 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02255 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-861 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-408 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7816 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7835 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-40 |
filingDate |
2019-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a89f060503b46bc4aafa94347c388760 |
publicationDate |
2020-04-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2020119149-A1 |
titleOfInvention |
Locos with sidewall spacer for transistors and other devices |
abstract |
An integrated circuit (IC) includes a first field-plated field effect transistor (FET), and a second field-plated FET, and functional circuitry configured together with the field-plated FETs for realizing at least one circuit function in a semiconductor surface layer on a substrate. The field-plated FETs include a gate structure including a gate electrode partially over a LOCOS field relief oxide and partially over a gate dielectric layer. The LOCOS field relief oxide thickness for the first field-plated FET is thicker than the LOCOS field relief oxide thickness for the second field-plated FET. There are sources and drains on respective sides of the gate structures in the semiconductor surface layer. |
priorityDate |
2018-10-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |