http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2020105356-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L2209-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-4402 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09C1-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L9-3278 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C17-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C17-18 |
| filingDate | 2018-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_edfe699425a7c763ec66aaa49c16416e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c29d5e3f5457120567bb44e5557918ee http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c92f84aa3c72a5dad0e1a305b423773c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_be48afa0ce863757b4b68b22b1bc89b3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_87ef6cd36c99ca2b96e70524113a25d2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6500f02d5ae988ec2b1de8d0a6026d11 |
| publicationDate | 2020-04-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2020105356-A1 |
| titleOfInvention | Hot carrier injection fuse memory |
| abstract | Memory cell circuitry is disclosed. The memory cell circuitry includes a first transistor configured to have a threshold voltage of the first transistor modulated by hot carrier injection, a second transistor coupled to the first transistor and configured to have a threshold voltage of the second transistor modulated by hot carrier injection, a word line coupled to a gate of the first transistor and to a gate of the second transistor, a first bit line coupled to the first transistor and a second bit line coupled to the second transistor. In addition, the memory cell circuitry includes a source line coupled to the drain of the first transistor and to the drain of the second transistor, the word line and the source line configured to cause hot carrier injection (HCI) into the first transistor when a first supply voltage is applied to the word line and the source line, and the second bit line is floated and the first bit line is grounded. The word line and the source line are configured to cause hot carrier injection into the second transistor when the first supply voltage is applied to the word line and the source line, and the first bit line is floated and the second bit line is grounded. Methods utilizing this technology for generating a multi-time programmable non-volatile memory and a random number generator for physical unclonable function applications are included in this disclosure. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112511308-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-4184513-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022031378-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11546177-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11405223-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10847236-B2 |
| priorityDate | 2018-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 70.