| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9047b16961c0aee78d7de367969339b2 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2254
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0409
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1157
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5671
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-26 |
| filingDate |
2019-03-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_189a8fd35e44d13ba21357d7ce15b2f5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_353eb0e6e324e2eab746aaf45a30e0ad
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8c0c732c930816bf4ebc99e739ab3ac7 |
| publicationDate |
2020-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2020090762-A1 |
| titleOfInvention |
Memory system |
| abstract |
According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022005537-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11768634-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11727996-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11513735-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11756642-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11605440-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11468953-B2 |
| priorityDate |
2018-09-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |