http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2020066912-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66628 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41733 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78693 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-45 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-221 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66742 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78618 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66969 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-221 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate | 2016-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_96ea2857905ffbb5901a3e708d502e7c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8e980122b0937ebb79125f5638c94801 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_74b593d93367e812acae50a26a4ae96c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f67b0212f6fd1b4f0e5143f7afd92ad http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_59ca49103cefb08cdea0a99ccb44955c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4aa3687e52eb202e0b96200b5878f62a |
| publicationDate | 2020-02-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2020066912-A1 |
| titleOfInvention | Systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in source and drain for low access and contact resistance of thin film transistors |
| abstract | In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors. For instance, there is disclosed in accordance with one embodiment a semiconductor device having therein a substrate; a bi-layer oxides layer formed from a first oxide material and a second oxide material, the first oxide material comprising a semiconducting oxide material and having different material properties from the second oxide material comprising a high mobility oxide material; a channel layer formed atop the substrate, the channel layer formed from the semiconducting oxide material of the bi-layer oxides layer; a high mobility oxide layer formed atop the channel layer, the high conductivity oxide layer formed from the high mobility oxide material of the bi-layer oxides layer; metallic contacts formed atop the high mobility oxide layer; a gate and a gate oxide material formed atop the high mobility oxide layer, the gate oxide material being in direct contact with the high mobility oxide layer; and spacers separating the metallic contacts from the gate and gate oxide material. Other related embodiments are disclosed. |
| priorityDate | 2016-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 77.