| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41741
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate |
2019-10-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a98778a8da1a48147ab1d621c2294365
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0a95c00f24197c9000c1fa5b13d43cb3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_888bf566a40c41db8955127fd1def57c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6bc5c5f45af232f10ee777d2fdc7d16d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d05f1f86d9fa7250567755f12c7d0d53
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0d45ae67a3070708aae779a38cc3ed4a |
| publicationDate |
2020-02-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2020052096-A1 |
| titleOfInvention |
Self-aligned contact for vertical field effect transistor |
| abstract |
Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2020052079-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11688775-B2 |
| priorityDate |
2017-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |