http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2020020806-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c8fbf590463d3518a746d90a6a2c1c34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5e829b93e1bdf87272f2aaf3baaaa0f4 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7836 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02107 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02008 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823468 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823835 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823864 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 |
| filingDate | 2019-09-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_95a57ca62a8d84a18a6f7d56efe85f22 |
| publicationDate | 2020-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2020020806-A1 |
| titleOfInvention | Semiconductor device and manufacturing method therefor |
| abstract | The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate structure, where the substrate structure includes: a substrate having a first device region and a second device region, a first dummy gate structure at the first device region, a second dummy gate structure at the second device region, and an LDD region below the first dummy gate structure. The first dummy gate structure includes a first dummy gate dielectric layer at the first device region, a first dummy gate on the first dummy gate dielectric layer, and a first spacer layer at a side wall of the first dummy gate. The second dummy gate structure includes a second dummy gate dielectric layer at the second device region, a second dummy gate on the second dummy gate dielectric layer, and a second spacer layer at a side wall of the second dummy gate. The method further includes removing the first dummy gate; etching back the first spacer layer to reduce a thickness of the first spacer layer; removing an exposed portion of the first dummy gate dielectric layer to form a first trench; and removing the second dummy gate and exposed second dummy gate dielectric layer to form a second trench. |
| priorityDate | 2016-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.