| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-324
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02381
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30625
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76202
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02579 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-324
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417 |
| filingDate |
2019-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_061da3a463120a07f42a5c5226a5d21d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_90ac7309258243c4e7bb2c65d3803949
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d0e95ccc9f675b9c134ab00549da69dd |
| publicationDate |
2020-01-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2020006484-A1 |
| titleOfInvention |
Integrated Circuit Structure With Non-Gated Well Tap Cell |
| abstract |
The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tape cell surrounding the IC cell; forming first fin active regions in the well tape cell and second fin active regions in the IC cell; forming a hard mask within the well tape cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tape cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tape cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tape cell. |
| priorityDate |
2018-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |