| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c63bc5ef3ae590b0603de4587961cac3 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4087
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-419
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4096
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4094
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4093 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-408
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-109 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate |
2018-10-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e5d9f4973e768bdf3710a84d6ce16002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c00795f9b0f21963e7d1974cc9d755bd |
| publicationDate |
2019-10-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2019325929-A1 |
| titleOfInvention |
Semiconductor devices |
| abstract |
A semiconductor device includes a column operation control circuit and a bank column address generation circuit. The column operation control circuit generates first and second bank address control signals as well as first and second bank control pulses from first and second bank selection signals in response to a synthesis control pulse such that data in a first bank and data in a second bank are simultaneously outputted in a first mode. The bank column address generation circuit generates first and second bank column addresses for selecting the first and second banks from a column address in response to the first and second bank address control signals. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11037609-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11211112-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10902894-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10593386-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2020082854-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10861512-B2 |
| priorityDate |
2018-04-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |