| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a04ec82c01a5765a0fb9c6c0d8a9abba |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-21 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M13-098
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M13-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17764
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-3177
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31724
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-1776
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-52 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3177
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M13-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-317 |
| filingDate |
2019-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8eb3297b8a83ca02d61432a8e8d80b94 |
| publicationDate |
2019-07-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2019227867-A1 |
| titleOfInvention |
Method and apparatus of using parity to detect random faults in memory mapped configuration registers |
| abstract |
A fault detection circuit generates a current parity bit for configuration data currently stored in a configuration register during each clock cycle, and compares the current parity bit with a previous parity bit generated during a previous clock cycle. An error signal is asserted when a mismatch is detected, indicating that the configuration register data erroneously changed due to a random hardware fault. Detection output circuitry is used to disable the error signal output driver using existing register input control signals, which prevents false error signals during intentional configuration data update operations. A parity input multiplexer, also controlled in response to the existing register input control signals, facilitates a parity update mode during intentional configuration data update operations, whereby updated parity values are generated for new/updated configuration data bytes before being written into the configuration registers. An optional self-test procedure verifies correct operation of the fault detection circuit. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021036690-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023020586-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112346783-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11626870-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112948167-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023136867-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11599411-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2023222026-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022043705-A1 |
| priorityDate |
2018-01-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |