http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019092633-A1

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filingDate 2018-09-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_83ee57e7824fd8a0cd4420f9685fe5b2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_81f0532487a5e1698f13d47f246b24b3
publicationDate 2019-03-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2019092633-A1
titleOfInvention Method to reduce pore diameter using atomic layer deposition and etching
abstract Methods are provided for manufacturing well-controlled, solid-state nanopores and arrays of well-controlled, solid-state nanopores by a cyclic process including atomic layer deposition (ALD), or chemical vapor deposition (CVD), and etching. One or more features are formed in a thin film deposited on a topside of a substrate. A dielectric material is deposited over the substrate having the one or more features in the thin film. An etching process is then used to etch a portion of the dielectric material deposited over the substrate having the one or more features in the thin film. The dielectric material deposition and etching processes are optionally repeated to reduce the size of the features until a well-controlled nanopore is formed through the thin film on the substrate.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11674947-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10994991-B2
priorityDate 2017-09-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 30.