Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5e829b93e1bdf87272f2aaf3baaaa0f4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c8fbf590463d3518a746d90a6a2c1c34 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-266 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66803 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-266 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7853 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0276 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0332 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8232 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31127 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-266 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-033 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-027 |
filingDate |
2018-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3b5599dae8c4198f4da87507ff1ef4ee http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_21cef560d8461431dc8d4435191a6329 |
publicationDate |
2019-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2019067127-A1 |
titleOfInvention |
Semiconductor structure and fabrication method thereof |
abstract |
Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a first region and a second region; forming a first filling layer on the first region of the base substrate and a first hard mask layer on the first filling layer; performing a first treatment process on the second region of the base substrate using the first hard mask layer and the first filling layer as a mask; forming a second filling layer on the first region of the base substrate and a second mask on at least the second filling layer; removing the first hard mask layer and the first filling layer to expose the first region of the base substrate and to pattern the second hard mask layer on the second filling layer; and performing a second treatment process on the first region of the base substrate. |
priorityDate |
2017-08-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |