| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42372 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate |
2016-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5a613dec8916f7a3150cdaee60c54f19
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e01978a16ddd2b150bbf262b5c1dec26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_47ffd34e22b998695ce7c26ca5d8df06 |
| publicationDate |
2019-01-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2019019793-A1 |
| titleOfInvention |
Transistor threshold voltage variation optimization |
| abstract |
One embodiment provides an apparatus. The apparatus includes a first transistor and a second transistor. The first transistor includes a first drain, a first source coupled to the first drain by a first channel, and a first gate stack comprising a plurality of layers. The second transistor includes a second drain, a second source coupled to the second drain by a second channel, and a second gate stack comprising a plurality of layers. Each gate stack includes a work function material layer to optimize a threshold voltage variation between the transistors. |
| priorityDate |
2016-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |