| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B61-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-228 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-01
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-85
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-12 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-22 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-08 |
| filingDate |
2018-07-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_47d84e6f4aeebc41969c26560104a9d9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a999ecc364bef8c06d1aeec7b1bbda16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9b7ddad00b45e482462385f6832b5f88
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7a7c1fece48afb3d6432b537ce2b2059
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d714146bf7ccb2fd456ede989ab42d27 |
| publicationDate |
2018-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2018351080-A1 |
| titleOfInvention |
Magnetoresistive random access memory device and method of manufacturing the same |
| abstract |
In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10714681-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-112020003521-B4
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2020127194-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11195993-B2 |
| priorityDate |
2015-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |