| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4175
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7787
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-778
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate |
2017-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_be9b5267a31086e6b0dfb8e507fa2b21
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c46cea55b7ea88d87c7ac8310a4c95e8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34c35777f1fc58d6907c9c2396669954
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6cfb79fc6f8adbac7abb3eeabc8748ec
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5793b5a796644757977984b18b120b66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ad100e287eb276d199461f34e3b8bccb |
| publicationDate |
2018-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2018337093-A1 |
| titleOfInvention |
Method for forming group iii-v device structure |
| abstract |
Methods for forming a group III-V device structure are provided. A method includes forming a first through via structure penetrating through group III-V compound layers over a front surface of a semiconductor substrate. The method also includes thinning the semiconductor substrate from a back surface of the semiconductor substrate. The method further includes etching the semiconductor substrate from the back surface to form a via hole substantially aligned with the first through via structure. In addition, the method includes etching the semiconductor substrate from the back surface to form a recess extending from a bottom surface of the recess towards the first through via structure. The first through via structure is exposed by the via hole and the recess. The method also includes forming a conductive layer in the via hole and the recess to form a second through via structure connected to the first through via structure. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-4246563-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10985084-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-4145497-A3
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10446472-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019027426-A1 |
| priorityDate |
2017-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |