| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B20-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0603
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66484 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2017-04-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eab04d970549ef9458baa933a5c4693c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b216a1fbec3e4bdacbad393880bc2188
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_337c73316e986c8c90bc56901d0a2631
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb |
| publicationDate |
2018-10-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2018286977-A1 |
| titleOfInvention |
Vertical transistor with back bias and reduced parasitic capacitance |
| abstract |
A method of making a vertical transistor device includes forming a front gate and a back gate opposite a major surface of a substrate. The front gate and the back gate are symmetric and arranged on opposing sides of a channel between the front gate and the back gate. The channel extends from a drain to a source. The method includes disposing a mask to cover the front gate and removing the back gate. The method further includes replacing the back gate with a layer of insulator and another back gate stack. The another back gate stack only covers a junction between the channel and the source, and remaining portions of the back gate are the layer of insulator. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2020303460-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11706932-B2 |
| priorityDate |
2017-04-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |