http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018189441-A1

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F17-5081
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filingDate 2018-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e3e3e0e2a450375b8c45205fd01f1431
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publicationDate 2018-07-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2018189441-A1
titleOfInvention Checking wafer-level integrated designs for antenna rule compliance
abstract Methods and systems for checking a wafer-level design for compliance with a rule include identifying nets that cross chip boundaries for each of a set of chip layouts. Interconnected identified nets are combined into one or more virtual ensembles having properties defined by a sum of properties of the respective interconnected nets. Chip layouts related to virtual ensembles that do not comply with a design rule are modified to bring non-compliant virtual ensembles into compliance.
priorityDate 2016-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 22.