Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02P90-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2119-18 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F17-5081 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F17-5072 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-392 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-39 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-398 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-367 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-50 |
filingDate |
2018-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e3e3e0e2a450375b8c45205fd01f1431 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e39255a9a630a815f181d6720f8abddc |
publicationDate |
2018-07-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2018189441-A1 |
titleOfInvention |
Checking wafer-level integrated designs for antenna rule compliance |
abstract |
Methods and systems for checking a wafer-level design for compliance with a rule include identifying nets that cross chip boundaries for each of a set of chip layouts. Interconnected identified nets are combined into one or more virtual ensembles having properties defined by a sum of properties of the respective interconnected nets. Chip layouts related to virtual ensembles that do not comply with a design rule are modified to bring non-compliant virtual ensembles into compliance. |
priorityDate |
2016-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |