| abstract |
In a split-gate-type MONOS memory, increase in a defective rate due to variation in a gate length of a memory gate electrode is prevented, and reliability of a semiconductor device is improved. A first dry etching having a high anisotropic property but a low selection ratio relative to silicon oxide is performed to a silicon film, and then, a second dry etching having a low anisotropic property but a high selection ratio relative to silicon oxide is performed thereto, so that a control gate electrode composed of the silicon film is formed, and then, a sidewall-shaped memory gate electrode is formed on a side surface of the control gate electrode. In this case, respective etching amounts of the first dry etching and the second dry etching are controlled by determining a length of etching time in accordance with desired characteristics of a manufactured memory and a film thickness of the silicon film in the first dry etching, based on an etching time setting table, so that a gate length of the memory gate electrode is controlled. |