| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3c754156d9ab873a2efe5a3990dbf627 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-124
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1248
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78618
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K59-1315
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41733
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66969
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66742
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1259
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66765
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-535
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K59-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K71-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-535
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 |
| filingDate |
2018-02-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_47a675484efe184af725c2e7310182dc |
| publicationDate |
2018-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2018166466-A1 |
| titleOfInvention |
Pixel structure and fabrication method thereof |
| abstract |
A pixel structure and a fabrication method thereof are provided, and the fabrication method includes steps as follows. A gate and a scan line connected to the gate electrode are formed on a substrate. An insulation layer is formed on the substrate and is patterned to form an opening corresponding to the gate electrode. A gate insulation layer is formed to cover the gate electrode and the scan line. A channel layer is formed on the gate insulation layer and is located in the opening. A first ohmic contact layer and a second ohmic contact layer are formed on the channel layer and are located in the opening. A source electrode, a drain electrode and a data line connected to the source electrode are formed on the first ohmic contact layer and the second ohmic contact layer. A first electrode is formed and is electrically connected to the drain electrode. |
| priorityDate |
2016-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |