| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8d629238b5c0aada2fc57fa5dbb59a41 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0332
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3086
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31055
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26586
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76811
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G03F7-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0276
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0274
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G03F7-201 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-308
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-027
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-265 |
| filingDate |
2017-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_05878111ccafae85965bd88d2c019ef2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0df110637e6b96753a43cbb14310cbd1 |
| publicationDate |
2018-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2018144941-A1 |
| titleOfInvention |
Methods and Apparatus for Fabricating IC Chips with Tilted Patterning |
| abstract |
The present disclosure describes methods and apparatuses for fabricating integrated-circuit (IC) die with tilted patterning. In some aspects, mandrels are fabricated on a material stack and occlude portions of a layer of material from a field of energy radiated at an angle of incidence relative to the mandrels. The occluded portions of the layer of material can be used to mask an underlying film to create a film pattern on a substrate of the IC die. These methods and apparatuses may enable the fabrication of IC die with features that are smaller in size than those afforded by conventional lithography processes. |
| priorityDate |
2016-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |