Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_68902f46d31f7b540653a398ef6058c3 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2207-481 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4022 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-504 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4282 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-525 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-52 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-4824 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-42 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-48 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-504 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-52 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-40 |
filingDate |
2017-11-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b07822a3d9f96800ff0867d4bb8f51de http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_299dfb9df312ca164e28464968b909bb |
publicationDate |
2018-05-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2018129475-A1 |
titleOfInvention |
Bit-serial multiplier for fpga applications |
abstract |
A Field-Programmable Gate Array (FPGA) implementation of a multiplier topology can provide a considerable increase in computation performance and cost benefit as compared to other approaches, particularly for large bit widths (e.g., for multiplication of large-bit numbers). A lack of sufficient input/output (I/O) ports on the FPGA for a particular bit width can be remedied by implementing large-bit number multiplications in a bit-serial fashion. The bit-serial multiplier topologies described herein can provide a relatively small footprint as compared to other approaches. An FPGA-implemented bit-serial multiplier can improve operation of a computing system, for example, by offloading binary multiplication operations from a general-purpose processor. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11106437-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11144286-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11709681-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11113176-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11275568-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021165945-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023138656-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10482209-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11567554-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11093682-B2 |
priorityDate |
2016-11-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |