| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
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| classificationCPCInventive |
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-702
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-025 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4096
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-18 |
| filingDate |
2016-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fa2f4630ee5455d912f053eef7b9a58d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7161f8736c5f18eabdf9a40341579bd7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_edfe699425a7c763ec66aaa49c16416e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_63d861555d17dc806a4b284df3dceca9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_96c75b1e69af1f3cb04e1e0eac5f7d5c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1887ac8a04a21df880b9206977c2c991 |
| publicationDate |
2018-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2018096971-A1 |
| titleOfInvention |
Systems, methods, and apparatuses for implementing die recovery in two-level memory (2lm) stacked die subsystems |
| abstract |
In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems. For instance, there is disclosed in accordance with one embodiment a stacked semiconductor package having therein: a processor functional silicon die at a first layer of the stacked semiconductor package; one or more memory dies forming a corresponding one or more memory layers of the stacked semiconductor package; a plurality of Through Silicon Vias (TSVs) formed through the one or more memory dies, wherein each of the plurality of TSVs traverse through the one or more memory layers to the processor functional silicon die at the first layer of the stacked semiconductor package; a plurality of physical memory interfaces electrically interfacing the one or more memory dies to the processor functional silicon die at the first layer through the memory layers via the plurality of TSVs; a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the processor functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV. Other related embodiments are disclosed. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11488945-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10666264-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2020086383-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10707197-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10949365-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019164856-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10840240-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11043952-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-3871257-A4
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10748874-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11764212-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11114416-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10991684-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10763181-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11531621-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019213152-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10910366-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10884956-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11379398-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I718706-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017109297-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11688734-B2 |
| priorityDate |
2016-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |