| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14634
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76832
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-24147
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-8203 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-146 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2017-11-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2647d07897fe58116ad0a3c938026bc0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1595f85d8cf0816fa1a029c8ed505a61
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_70d680d1c5c82013f7aed01fdcfd7259
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_407506b200107d062df888a878731a9a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0b16292891b398a2da79b57a8674d4c2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e110bb34d69ffba16c68b3ba2e151a9b |
| publicationDate |
2018-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2018082928-A1 |
| titleOfInvention |
Manufacuting method of semiconductor structure |
| abstract |
The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 μm to about 0.2 μm. |
| priorityDate |
2014-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |