| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1104 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0332
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate |
2017-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aefb7fada7091f998d85ade2ed3d6397
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4b4e3b73741e0925e5b710b3b0c5f086 |
| publicationDate |
2017-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2017345819-A1 |
| titleOfInvention |
Semiconductor device having gate structure with reduced threshold voltage and method for manufacturing the same |
| abstract |
A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N 2 )-based silicon nitride (SiN) which is free of OH concentration. |
| priorityDate |
2016-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |