| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1608
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42368
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7854
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2017-07-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7c060f05cb35101de1a986060eb8d038
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_632c4a89c5169223793e063afe6a4079
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_21e2ec7581223f9dd5d0a1b11183a4ee
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1d80a5f9d37f9e82b423037c2d79945e |
| publicationDate |
2017-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2017338348-A1 |
| titleOfInvention |
Flat sti surface for gate oxide uniformity in fin fet devices |
| abstract |
Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile by the thermal hydrogen treatment. |
| priorityDate |
2015-08-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |