| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_323834c4243d986e53b08d8849f9664e |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28587
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42316
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-778
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-285
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 |
| filingDate |
2017-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c5e860ee909916bccba6cb3b598c162c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bd4b86efca9b5b2fe67b5d04c8ba7ff7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5176010ea3a1f1bd59391388651254cf |
| publicationDate |
2017-11-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2017317179-A1 |
| titleOfInvention |
GATE WITH SELF-ALIGNED LEDGE FOR ENHANCEMENT MODE GaN TRANSISTORS |
| abstract |
An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10720506-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-3686935-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11114537-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10784336-B2 |
| priorityDate |
2009-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |