patent/US-2017170312-A1

http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017170312-A1

Outgoing Links

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assignee	http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_90abf0edd17ab0a899f77fba323967c8
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classificationIPCInventive	http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-40
filingDate	2015-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor	http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_badeaa835beafb95ff5625372070c0f5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5fb02b77658fef3f4f75be00244ae6c3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2fb945a48b30fc5fb29d748dfef67625
publicationDate	2017-06-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber	US-2017170312-A1
titleOfInvention	High voltage dmos and the method for forming thereof
abstract	A high voltage DMOS device using conventional silicon BCD (Bipolar CMOS DMOS) technology has a P-type buried layer and an N-type buried layer, a first epitaxial layer and a second epitaxial layer. The high voltage DMOS device is characterized in high breakdown voltage, good robustness and low Ron through controlling the thickness of the epitaxial layers, the dose and forming energy of the buried layers. In addition, the high voltage DMOS may further has a shallow drain region to further improve robustness.
isCitedBy	http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-3712953-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10714594-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11349000-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11552183-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019148517-A1
priorityDate	2015-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type	http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 40.