http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017170179-A1

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filingDate 2016-05-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5b03e9ba0248a16b700dabd53a209919
publicationDate 2017-06-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2017170179-A1
titleOfInvention Spacer for dual epi cmos devices
abstract Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor. The method also includes etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process.
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