| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e3d6fa926ef6ac3947565c2d90afae18 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02E10-50 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-0516
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-02021
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02118
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-02008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5386
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76871
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-061
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-022441
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-1876 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-061
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-02 |
| filingDate |
2016-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a6e01ec3794b45c12c2f59401a38a039
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3e976b1b58c703e0e03c237c3e9d96e9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b8d8031877a28eeeb1e300449b397c49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dd03ff9c777ff8167b66a995ef581b3e |
| publicationDate |
2017-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2017162724-A1 |
| titleOfInvention |
Fast process flow, on-wafer interconnection and singulation for mepv |
| abstract |
A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11502213-B2 |
| priorityDate |
2014-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |