| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5256
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B20-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11206
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0629
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0617
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-112
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-525 |
| filingDate |
2016-11-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eda712488d48d4f595a307b2b23e78e7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d541cd51f692d871430236d37e9436f3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_53a1c4fcf706dda08d7bb5e55a845065 |
| publicationDate |
2017-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2017062335-A1 |
| titleOfInvention |
Integrated circuit with electrical fuse and method of forming the same |
| abstract |
A method of forming an integrated circuit. The method includes forming at least one transistor and at least one electrical fuse over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate and a work-function metallic layer over the gate dielectric structure. Forming the at least one transistor further includes forming a conductive layer over the work-function metallic layer and a source/drain (S/D) region being disposed adjacent to each sidewall of the gate dielectric structure. Forming the at least one transistor further includes forming a diffusion barrier layer between the gate dielectric structure and the work-function layer. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. Forming the at least one electrical fuse includes forming a first silicide layer on the first semiconductor layer, wherein the diffusion barrier layer is formed before the first silicide layer. |
| priorityDate |
2011-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |