| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-3656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-267
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L43-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2201-88 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31701
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-3177
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318538
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318544
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31723
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31713
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318533
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31727
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-22 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-317
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3177 |
| filingDate |
2016-11-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_49c225d1d762d4706fc7ee1f1d6ba8e2 |
| publicationDate |
2017-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2017059654-A1 |
| titleOfInvention |
Alternate signaling mechanism using clock and data |
| abstract |
Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state. |
| priorityDate |
2008-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |