| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C2203-037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C2203-0792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2201-0242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2207-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2201-0264
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2201-0235
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2207-012
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C2203-035
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2203-0315
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C2201-0132 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B7-007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B3-001
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C3-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-83
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C1-00238 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B81C1-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B81B7-00 |
| filingDate |
2016-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2da6d3245e11e67c16205e4873c25006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_05c4edfac0da9be96783c74395073f22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_341dc86485d4ab18e1eae605a79dd860 |
| publicationDate |
2017-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2017057814-A1 |
| titleOfInvention |
Mems and cmos integration with low-temperature bonding |
| abstract |
The present disclosure relates an integrated chip having one or more MEMS devices. In some embodiments, the integrated chip has a carrier substrate with one or more cavities disposed within a first side of the carrier substrate. A dielectric layer is disposed between the first side of the carrier substrate and a first side of a micro-electromechanical system (MEMS) substrate. The dielectric layer has sidewalls that are laterally set back from sidewalls of openings extending through the MEMs substrate to the one or more cavities. A bonding structure, including an intermetallic compound having a plurality of metallic elements, abuts a second side of the MEMS substrate and is electrically connected to a metal interconnect layer within a dielectric structure disposed over a CMOS substrate. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10745271-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11342266-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10472233-B2 |
| priorityDate |
2014-11-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |