| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bb68097a7397e9e28e05de7be758d66e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2201-055
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2201-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61B5-14514 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01L9-0042
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823878
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01P15-125
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01L9-0054
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C1-00246
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76254
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03H3-0073
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01P15-0802 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate |
2014-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_800c6f8c058efadc49bee779503f6db3 |
| publicationDate |
2017-01-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2017011972-A9 |
| titleOfInvention |
Method and structure of three dimensional cmos transistors with hybrid crystal orientations |
| abstract |
A method for fabricating a three-dimensional integrated circuit device includes providing a first substrate having a first crystal orientation, forming at least one or more PMOS devices overlying the first substrate, and forming a first dielectric layer overlying the one or more PMOS devices. The method also includes providing a second substrate having a second crystal orientation, forming at least one or more NMOS devices overlying the second substrate, and forming a second dielectric layer overlying the one or more NMOS devices. The method further includes coupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate. |
| priorityDate |
2008-07-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |