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Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02433
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0254
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02381 |
| classificationCPCInventive |
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003
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| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03F3-213
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
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| filingDate |
2016-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f67b0212f6fd1b4f0e5143f7afd92ad
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5e09485f7c1907393b48938dc7b6d297
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b4b37c55314f2162dd29203de7b4693e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_01256746433fa298de5e1db9f79f600b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dc268ad00546a86c3211f9cd5314d59e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c8f669b22612d950a2e1bea3b64867b6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d7a5c53cc886427c0f191656e3694f6b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6dcc9e402148133048ff83796112700c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8e980122b0937ebb79125f5638c94801 |
| publicationDate |
2016-11-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2016343844-A1 |
| titleOfInvention |
Non-planar iii-n transistor |
| abstract |
Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (10 1 0) plane on a (110) plane of the silicon. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-7099480-B2 |
| priorityDate |
2011-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |