| abstract |
A thin film transistor array panel, including a substrate; a gate electrode on the substrate; a semiconductor layer on the substrate; a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer including a first oxide insulating layer in contact with the semiconductor layer; a source electrode on the semiconductor layer; a drain electrode facing the source electrode; and a passivation layer covering the source electrode and the drain electrode, the passivation layer including a second oxide insulating layer in contact with the source electrode and the drain electrode, at least one of the first oxide insulating layer and the second oxide insulating layer having a varying hydrogen content distribution in a thickness direction. |